1. Field of the Invention
The present invention relates to the field of semiconductor electrically programmable and electrically erasable read-only memories (EEPROMs) and to electrically programmable read-only memories (EPROMs) having floating gates, and more particularly to a new method for multi-level cell writing.
2. Description of Related Art
The most commonly used EPROM cell has an electrically floating gate which is surrounded by insulation and generally disposed between a source and drain region formed in a silicon substrate. In earlier versions of these cells, charge is injected through the insulation by avalanche injection. Later versions of EPROMs relied on channel injection for charging the floating gate. These EPROMs are erased by exposing the array to ultraviolet radiation.
Electrically erasable EPROMs (EEPROMs) are also very common. In some cases, charge is placed into and removed from a floating gate by tunneling the charge through a thin oxide region formed on the substrate. In the other instances, charge is removed through an upper electrode.
Another type of common EPROM/EEPROM is referred to as Flash EPROM or Flash EEPROM. In these flash memories, the entire array is simultaneously erased, electrically.
FLASH EPROM: The structure of this device is the same as that of traditional ultraviolet erasure-type EPROM. Programming can be performed by hot electron injection from the channel. The cell is programmed to a high cell threshold voltage, V.sub.t, by means of channel hot electron injection, with the control gate and the drain connected to a high voltage. Erasing the cell to a low threshold state is performed by Fowler-Nordheim tunneling of electrons from the floating gate to the source diffusion layer by grounding or applying a negative voltage to the control gate and applying a high voltage to the source diffusion.
FLASH EEPROM: In contrast to the Flash EPROM devices, these devices use drain edge Fowler-Nordheim tunneling to erase to a low cell threshold voltage, V.sub.t, by page with bit verification basis and use channel Fowler-Nordheim tunneling erase to a high cell threshold voltage, V.sub.t, by sector verification basis.
The first one of these two types suffers from erased-V.sub.t distribution control.
Electrical erase is not self-limiting. Therefore, electrical erase can leave the floating gate positively charged, thus turning the memory transistor into a depletion-mode transistor; this is called over-erasing.
A soft program is used to recover a limited number of over-erased bits and pre-programing is needed to avoid over-erasing of those bits subjected to erasure during program/erase cycle.
The second one of these two types of NOR flash memories, which controls the low cell V.sub.t distribution by bit-by-bit verification with a page bit-latch system, suffers from high band-to-band tunneling induced hot-hole damage, which causes data retention, as to keep the program speed compatible with hot-channel-electron programming system.
Holes can be generated through surface-field-induced band-to-band tunneling in the source-to-gate overlap region. These holes first travel parallel to the substrate interface and then flow to the substrate. However, a significant number of these holes become energetic while traveling in the depletion region. These hot holes can surmount the Si/SiO2 barrier and inject into the oxide. This situation is most frequently encountered in the electrical erase operation of the flash memory cell.
Hot hole injection during flash erase has been identified as a major concern for cell performance and reliability. Hot hole injection could cause variation in the erased cell V.sub.t in the memory array as well as the generation of surface states in the cell channel region.
Moreover, these two systems mentioned above have high sector size, which may seriously limit their application domain and deteriorate the endurance of flash EEPROM cells because of multiple program/erase cycles for minor data changes in the same sector.
Another problem associated with floating gate memory devices arises because the charging and discharging of the floating gates is difficult to control over a large array of cells. Thus, some of the cells program or erase more quickly than others in the same device. In a given program or erase operation, not all the cells subject of the operation will settle with the same amount of charge stored in the floating gate. Thus, so-called program verify and erase verify sequences have been developed to efficiently ensure that the memory is being accurately programmed and erased. The program and erase verify operations are based on comparing the data stored in the floating gate memory array with the intended data. The process of comparing data is relatively time consuming, involving sequencing byte by byte through the programmed or erased cells. If a failure is detected in the verify sequence, then the program or erase operation is retried. Program retries are typically executed word-by-word or byte-by-byte in prior art devices. Thus, bits successfully programmed in a byte with one failed bit are subject to the program cycle repeatedly. This can result in over-programming and failure of the cell.
To improve the efficiency of program and program verify operations, so-called page mode flash devices have been developed. In these devices, a page buffer is associated with the memory array. The page buffer includes a set of bit latches, one bit latch associated with each global bitline in the array. To program a page in the array, the page buffer is loaded with the data to be programmed, by transferring byte by byte the program data into the bit latches of the page buffer. The program operation is then executed in parallel on a bitline by bitline basis controlled by the contents of the bit latches. The verify procedure is based on clearing automatically all of the bit latches in the page buffer which are successfully programmed in a parallel operation. The page buffer is then read byte-by-byte to confirm that all bits have been cleared, indicating a successful program operation.
Some types of floating gate memory program or erase operations involve applying a high voltage to the bitlines.
An improved page buffer that operates with low current bit latches, and is capable of supporting program, program verify, read and erase verify processes in a page mode is desirable. Also, it is desirable that the page buffer be useful for applying high voltage pulses to bitlines based on the contents of the page buffer.